1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device of which an operation is controlled according to information stored in a nonvolatile memory element such as a fuse. The present invention further relates to a data processing system including the semiconductor device.
2. Description of Related Art
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a nonvolatile memory element is provided for a replacement of a defect address or an internal operation switching. The nonvolatile memory element includes an antifuse element that is electrically programmable and a laser fuse element that can be blown (disconnected) by an application of a laser beam. Information written in the nonvolatile memory element is read out by a readout signal, and it is stored in a latch circuit (see Japanese Patent Application Laid-open No. H8-96594).
Meanwhile, in some semiconductor devices such as a DDR3 (Double Data Rate 3) DRAM, a reset terminal is provided as an external terminal. An external reset signal is supplied to the reset terminal. When the external reset signal is activated, the latch circuit is reset and the information written in the nonvolatile memory element is read out. With this operation, information written in the nonvolatile memory element is correctly loaded to the latch circuit, and thereafter a semiconductor device is initialized. The reset signal is activated at the time of startup and at an arbitrary timing during the operation.
However, an application of a fuse circuit disclosed in Japanese Patent Application Laid-open No. H8-96594 to a semiconductor device including the above reset terminal can cause the following problem.
In Japanese Patent Application Laid-open No. H8-96594, a flip-flop 4 is reset in response to activation of a signal YRD from an ATD signal generating circuit 2, and a selected fuse F is read out across a period during which a signal YRDB is activated. According to this conventional technique, the fuse F is constantly read out in the period during which the signal YRDB is activated. At this time, as long as the selected fuse is in an electrically conductive state, a current keeps on flowing from a power source to a ground.
Accordingly, if the fuse circuit described in Japanese Patent Application Laid-open No. H8-96594 is applied to a semiconductor device including a reset terminal, a current keeps on flowing through an unblown (connected) fuse element across a period during which an external reset signal is activated. As a result, there is a problem that, for example, when the external reset signal is activated in a state that a low current consumption is required, such as a deep power down mode of a DRAM, the current consumption exceeds its regulated value.